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[CHIMES]

Welcome to this installment of

the TI Precision Labs series

on motor drivers.

My name is Pablo Armet,

and in this video,

I’ll be going over the best

PCB layout guidelines for motor

driver circuits.

This training video

will be broken down

into several sections,

and we’ll closely

follow the best practices for

board layout of motor drivers

application report listed

in the resources slide

at the end of the presentation.

First, I will discuss why

following proper layout

guidelines and having good

PCB layout is important.

Then, I will provide

best practices

to follow for optimizing

PCB grounding, improving

thermal performance

of the board,

how to choose and place vias,

general routing techniques,

bulk and bypass capacitor

placement, and power stage

routing and MOSFET placement.

Let’s begin by discussing

why having a good PCB layout

is extremely

important, especially

in motor driver applications.

While there are

many issues which

can occur due to

poor PCB layout,

I will cover a few of the most

common issues which can arise.

Poor PCB layout can

cause many issues,

such as poor thermal

performance, which

can lead to the motor

driver and other components

overheating and being

potentially damaged.

Another problem with

bad physical layout

is the increase of capacitor

and inductive coupling, which

can degrade signal integrity

and cause the circuit

to not operate as intended.

Increased common and

differential noise

was another issue caused

by poor PCB layout.

The following slide will

present proper layout guidelines

to follow to mitigate the

issues presented in this slide.

Implementing good

grounding techniques

is crucial to ensure a

stable reference voltage

is provided to the IC and its

surrounding circuit components

with noise and other isolations.

The two most common grounding

schemes are partition and grid.

In a partition

ground, the ground

for the digital, analog,

and high-power signals

are separated.

This separation ensures

that the noisy grounds

from the high-power

signals don’t

disrupt the sensitive

digital and logic signals.

In a grid ground

scheme, the ground pads

are continuous

throughout the board

to make sure each signal

has a low-impedance return

path to the source.

The appropriate grounding

technique to follow

depends on the

design application.

If the application

is for high power,

it is recommended to use

the partition ground scheme.

If the application is

for low- to mid-power,

the grid ground scheme

is generally recommended.

The left image shows

a grid ground scheme,

where the ground is common

between the digital and power

parts of the board.

The right image shows a

partition ground scheme,

where the digital or logic

ground and the power ground

are separated.

Note that there is no

complete physical separation

between the two grounds.

The two grounds are

connected at a single point,

which is indicated by the

orange lines in the image.

Aside from choosing the

appropriate ground scheme,

there are always general

grounding techniques

that should be followed

when designing a PCB layout.

It is strongly recommended to

have a continuous ground plane.

If the PCB is four

layers or more,

have one layer dedicated

as a ground plane

to ensure the signals

have the shortest return

path to the power source.

If the PCB is two

layers or less,

make sure that the amount of

ground copper on each layer

is maximized and continuous.

Route the signals and

place the component such

that their ground

area is maximized

and that there are no

areas of ground copper

that is physically separated

from the rest of the ground.

Also, ensure that the

ground plane discontinuity

is minimized.

This can be achieved by

carefully routing the traces,

reducing the amount

of vias when possible,

placing vias away

from each other,

and placing the components

such that the ground

plane is continuous

throughout the board.

In real-world

applications, motor drivers

are not ideal devices, and

much of its internal energy

is converted to heat.

This heat must be

effectively dealt

with before damage occurs to

the driver or any surrounding

components.

Proper PCB layout can

help disperse the heat

and keep the motor driver at

the recommended temperature.

To better understand how

to effectively disperse

the heat from the driver, it

is important to understand

the paths that the heat

travels from the driver.

The top-right image

shows different paths

that the heat takes

from the driver.

The paths are represented

by the red arrows.

The larger the

arrow, the more heat

that travels through that path.

As can be seen in the

image, most of the heat

travels down from the

thermal pad of the IC

and spreads out through the

internal and external layers

of the board.

Some heat travels

from the bonding wires

and through the leads

to the top layer traces.

Another portion of the heat

is dissipated to the open air

outside of the PCB.

To ensure that the heat spreads

evenly throughout the PCB

and is not concentrated

near the driver,

here are some layout

techniques to follow.

If the IC has a

thermal pad, make sure

that the top layer copper

pour from the thermal pad

to the grounding

planes are continuous.

The middle-right

images show the impact

on thermal performance

of a continuous pour

versus a discontinuous pour.

When the pour is

cut off by a trace,

heat is concentrated

near the IC, which

results in higher temperatures.

On the other hand, when

the pour is continuous,

the heat can easily flow

through both sides of the device

and reduce the

temperature near the IC.

Another technique to improve

thermal dissipation is to use

1.5-ounce or 2-ounce copper

pour for plating thickness.

Increasing the plating

thickness reduces

the effective

thermal resistance,

which increases the thermal

conductivity of the copper.

Another technique is to use

direct-connected thermal vias

instead of thermal relief vias.

The bottom-right image shows

a side-by-side comparison

of the thermal performance

of direct connect

and thermal relief vias.

The direct connect vias

allow for the lowest

possible thermal resistance

between the via and copper

layers, which helps achieve

the lower temperatures.

Lastly, it is recommended

to use a minimum 8 mil hole

size by 20 mil diameter

size thermal vias

directly beneath the thermal pad

for optimal heat conductivity.

Group the thermal

vias into arrays

near the regions of high

heat concentrations,

such as the thermal pad

and regions near the IC.

Vias are an essential

component in any layout design.

There are many types of vias,

but in this presentation,

we’ll be focusing on the

typical through-hole vias

since those are the most common

vias used in motor driver PCB

designs.

Here are some general guidelines

to follow when using vias.

Make sure the vias have solid

exposed copper area instead

of a spoke or web

exposed copper area.

The image labeled as 1

shows the two via types.

Solid vias have a more

continuous exposed copper area,

allowing the via to conduct

the current more efficiently.

Make sure to select the

appropriate via size

and quantity for the appropriate

current capacity needs.

The table labeled as 2

shows the current capacity

for different hole

diameter sizes.

The via diameter size should

be at least the same size

as the trace width.

The via diameter

size, or the number

of vias for a

given trace, should

be increased to allow

more current to flow

to the other layer.

If a power or ground plane

needs to be connected

to another layer, make

sure to use multi-vias

or via stitching.

Multi-vias and via

stitching are useful

for low-parasitic grounding

and high-current connections.

Image 3 shows an

example of multi-vias.

Lastly, don’t place vias

too close to each other.

Image 4 shows examples of good

and bad spacing between vias.

Having vias with good

separation allows

for the plane to

be more continuous

and for the signal

pad to be shortened.

This slide presents a few

important routing techniques

to follow when designing

a motor driver PCB layout.

The first technique is to

make sure the gate drive

traces are as wide and

as short as possible.

The recommendation is to start

with a trace width of 20 mils

for Szeastwin at least 1.5-ounce copper

plating thickness and increase

the width for higher currents.

For gate drivers,

route the single trace

of the high-side gate

and the switch node

trace as close as

possible to minimize

inductance, loop area, and

noise caused by fast changes

and voltage induced

by switching.

For motor drivers

with integrated FETs,

this routing is

optimized internally.

Do not use right-angle

traces, as it

can cause electromagnetic

interference issues.

The image labeled

as 1 shows examples

of different trace angles and

ranks them from best to worst.

When possible,

always use a teardrop

technique when

transitioning from vias

to pads or from a

thin to a thick trace.

Using teardrop reduces

the thermal stress

of the single transition.

The images labeled as 2 shows

an example of a teardrop.

Route traces in parallel

pairs, otherwise

known as differential pairs,

when routing around an object.

For example, when routing the

signals from the current sense

amplifiers, make

sure that the traces

stay as close together

as possible to avoid

any differential impedance

and discontinuity

caused by split traces.

Image 3 shows a good and a bad

parallel pair routing example.

A last general

routing technique is

to have a separate grounding

for analog and digital parts

of the circuit to

reduce ground noise.

Image 4 shows an illustration

of the right and wrong routing

topology.

Bulk and bypass capacitors

are important components

in a motor driver design.

Bulk capacitors help reduce

the low-frequency current

transients and stores charge to

supply large currents required

by the motor system.

Bypass capacitors are used to

minimize the high frequency

noise into the supply

pin of the motor driver.

This slide will show

a few guidelines

to follow for selecting and

placing the various bulk

and bypass capacitors typically

used in a motor driver circuit.

Place all bulk capacitors

near the power entry

point of the board.

This will ensure that the

low-frequency transients

are suppressed before it

travels further into the PCB.

When selecting the

bulk capacitance,

always consider

the highest current

required by the motor

system, supply voltage

ripple, and the type of motor.

For drivers that have

integrated charge pumps,

place the charge pump

capacitors or bootstrap

capacitors as close to

the driver as possible.

This will ensure that

the trace inductance

impedance between the

capacitors and the charge

pump pins on the

driver is minimized.

High-trace inductive impedance

can cause unwanted oscillations

that can affect the

performance of the charge pump.

Make sure the local

bypass capacitors

are on the same layer

as the driver IC

and are close to the driver.

This is to ensure

that the signal

traces between the bypass

capacitors and the IC

are in the same layer

without the need

to use vias, which can increase

the inductance in the trace.

Image 1 shows a schematic

where the local bulk bypass

capacitors should be located.

Note that the capacitor

of the lower value

is placed closer to the IC.

Avoid placing vias between

the bypass capacitor

and the driver.

Vias will increase

the inductance

in the high-current

loop, which is not ideal.

Image 2 shows an example

of good and bad bypassing.

In the power stage, use

small ceramic capacitors

to attenuate high-frequency

transients that occur when

the edge bridge is switching.

Image 3 shows a schematic

of the power stage

and where the capacitor

should be placed.

Make sure to minimize

the high-frequency loops

as much as possible.

If the device has integrated

current-sensing amplifiers,

place filtering capacitors

near the sensing

pins to filter out

noise from the signal.

A capacitor of around one

nanofarad is recommended.

For devices with

voltage regulators,

small ceramic capacitors should

be placed near the regulator

output.

Always make sure to

minimize the ground return

loop to the ground

pin of the device.

Placement and PCB layout

of the power MOSFETs

is very important,

especially for gate drivers

to ensure correct functionality

in the motor driver system.

For devices with

integrated MOSFETs,

the layout and placement

is optimized internally.

This slide will show

a few basic layout

examples, based on common

motor driver architectures.

The most important

guideline to follow

is to place the

MOSFETs in such a way

that the area of the

high-frequency loops

is minimized.

Image 1 and 2 show

recommended layout examples

of half-bridge stack and

half-bridge side-by-side

configurations, respectively.

The left part of each image

shows a layout example

of lead-in MOSFET packages,

and the right part

shows a layout example of

non-leaded MOSFET packages.

Note that in both

examples, the MOSFETs

are placed very

close to each other

to reduce the

high-current loop area

and parasitic trace inductances.

The parasitic inductances

in the power stage

should be minimized to

reduce switch-node ringing

oscillations.

Switch-node ringing

is the OC oscillation

that occurs on the switch node,

which is a node where the motor

terminal is connected to.

These oscillations

are undesirable

and can cause high EMI noise and

create overshoot and undershoot

voltages, which can violate

absolute maximum ratings

of the MOSFET.

Image 3 shows common

parasitics, like the inductance

in the drain and source

traces found in a half-bridge.

The best way to minimize

switch-node ringing

is by careful PCB layout.

Use external measures,

such as reducing slew rate

or including

external RC snubbers

to minimize switch-node

ringing when needed.

The slew rate can be reduced

by placing a resistor

in the MOSFET gate, or by using

Texas Instruments Smart Gate

Drive technology that allows

for easy adjustment of the slew

rate.

Another solution to

minimize switch-node ringing

is placing a snubber

circuit between the drain

and the source of

each MOSFET, which

can help filter out the

undesirable oscillations.

As mentioned previously,

it is strongly

recommended to optimize

the PCB layout for reducing

the high-current loop path.

The high-current loop

in the power stage

is shown by the red

path in Image 4.

This loop path can be minimized

by using wide and short traces

and reducing the number of

layer jumps in the loop.

Thank you for viewing this

installment of the Texas

Instruments Precision Lab

Series on motor drivers.

To learn more about the topics

covered in this training video,

read the “Best Practices for

Board Layout of Motor Drivers”

application report that

is listed in the resources

slide of this presentation.

Also, to learn more about motor

driver technical resources

and browse Texas Instruments’

catalog of motor driver

products, please visit the

motor driver page on ti.com.

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